1. Field of the Invention
The present invention relates to a method for manufacturing a BiMOS (or BiCMOS) device.
2. Description of the Related Art
In a prior art method for manufacturing a BiCMOS device (see JP-A-4-346263), a heating operation for forming an emitter region of a bipolar transistor is carried out before the formation of source/drain regions of a MOS transistor. Therefore, the total time of heating operations after the formation of the source/drain regions can be reduced, or such heating operations can be at lower temperatures. Thus, the short channel effect of the MOS transistor can be suppressed. Also, the heating operation for forming the emitter region, i.e., the base-emitter junction can be sufficiently carried out. Further, since a relatively thick insulating layer is provided between the emitter electrode and the base region of the bipolar transistor, the parasitic capacitance of the emitter electrode can be reduced to improve the high frequency characteristics. This will be explained later in detail.
In the above-described prior art method, however, the reduction of the parasitic capacitance of the emitter electrode is insufficient.
Also, the above-described prior art method requires an additional process for thermally growing the insulating layer for reducing the parasitic capacitance of the emitter electrode, thus increasing the manufacturing cost.